Tezzaron’s 3T-iRAM® memory technology, based on the time-tested DRAM model, offers DRAM-like advantages in cost and density; however, its novel current-sensing process achieves SRAM-like performance. The name “3T-iRAM” comes from the three-transistor cell design plus the letter “i” — the engineering symbol for electric current — to represent the current-sensing technology employed.
The dramatic speed of 3T-iRAM® was achieved by re-designing the DRAM read mechanism to react to changes in current rather than changes in voltage. In memory circuits, the current changes more quickly than the voltage does, so changes in current can be detected more quickly than changes in voltage. By exploiting this difference, 3T-iRAM® technology can provide better-than-SRAM speed at a much lower cost.
3T-iRAM® chips incorporate another speed advantage. In many memory devices, some idle time is required in “turnaround” – that is, when a read command is followed by a write command, or vice versa, the memory “bus” is idle for one or more cycles. 3T-iRAM® chips require no idle time at all on turnaround; this contributes to their speed.
3T-iRAM® provides twice the capacity of standard SRAM in exactly the same footprint. The reason for this is simple: standard SRAM technology requires six transistors for each memory cell, but each 3T-iRAM® cell needs only three transistors.
Because 3T-iRAM® is built on DRAM technology, it shares DRAM’s reliability; like DRAM, it is more resistant to soft errors than SRAM.
Because 3T-iRAM® senses current rather than voltage, very precise measurements are possible. In fact, current can be measured with a precision six orders of magnitude greater than is possible with voltage. This raises the possibility of multi-bit cells – storing several bits in each cell at widely separated values, as is presently done with high-density Flash chips. 3T-iRAM’s® multi-bit cell design adds a capacitor to each three-transistor cell, but because the capacitor can overlap the transistors, it does not greatly increase the cell area. Each multi-bit cell can hold as many as eight bits; when combined with FaStack stacking, this enables capacities as large as 8 Gbit without increasing the footprint.
A: 3T-iRAM® is closer to DRAM, but it has some unique properties. It is dynamic in that refresh is required, but 3T-iRAM® reads are nondestructive (unlike DRAM reads). Whereas DRAM uses voltage deflection on a bit-line pair, 3T-iRAM® provides a real positive current drive. This positive drive reduces noise sensitivity and increases speed.
A: Yes, it generally is. The higher speed is mostly due to 3T-iRAM’s smaller cell size, lower bit-line capacitance, and better bit-line drive from the memory cells. Even with the addition of hidden refresh, 3T-iRAM® will perform at least as fast as SRAM, in a much smaller area, and using less power.
A: 1T SRAM provides a cell size similar to that of 3T-iRAM®, but 3T-iRAM® provides better speed – in fact, the speed of 1T SRAM is comparable to that of ordinary DRAM of the same array size.
A: Different types of SRAMs require different replacements. The first wave of stand-alone 3T-iRAM® parts, built in a standard CMOS logic process, can replace high-speed SRAMs. Another version of 3T-iRAM, already under development, is optimized for incorporation in an embedded DRAM process; this version will be better for replacing large, low-power SRAMs. The latter version will achieve lower power and higher density than is available with any DRAM or SRAM structure.
A: We have run 3T-iRAM® components in 0.5µm, 0.35µm, 0.25µm, 0.13µm, and 90nm processes.
A: Proprietary memory blocks that incorporate 3T-iRAM® technology have been in volume production since 1999. The first stand-alone memory prototype was produced in 2003.
A: Yes. Tezzaron has produced 3T-iRAM® components in no fewer than 5 different foundries and 6 different processes.
A: No. All 3T-iRAM® parts to date have used standard single poly CMOS processing. Tezzaron is in discussions with some manufacturers about higher-performance parts; if these are developed, they could require unique processing.
A: Yes. While Tezzaron has so far concentrated on maximum portability, 3T-iRAM® can easily be altered to run in a DRAM fabrication process.
A: 3T-iRAM® operating voltage depends on the process in which it is made. The 90nm prototype was designed for 1.2V operation, whereas the 0.5µm part previously created ran at 5V. In general, the lowest possible operating voltage is 2.5 to 3 times the threshold voltage (Vt).
A: Array efficiency is a measurement of how much area in a memory block is used by memory cells compared to the area used by drivers, sense amps, and other required support circuitry. The highest performance 3T-iRAM® has array efficiencies in the 75% range. Other versions of 3T-iRAM® (with somewhat slower performance) can reach efficiencies of 90%.
A: In a 90nm process, the 3T-iRAM® bit-cell size is 0.59 square µm. For a rough estimate in any process, a 3T-iRAM® bit-cell is just under 50% the size of an SRAM bit-cell.
A: 3T-iRAM® parts built in a standard CMOS process are less sensitive than standard SRAMs but more sensitive than DRAMs. Soft error sensitivity has a lot to do with the internal capacitance of the bit-cell: higher capacitance means lower susceptibility. 3T-iRAM® in a standard CMOS process has 2 to 4 times the storage node capacitance of a standard SRAM in the same process. Tezzaron is working on a version of 3T-iRAM to be built in an embedded DRAM process. Among other significant benefits, this version should have a lower soft error rate than competitive standard DRAM solutions.
A: Yes. 3T-iRAM® is easily adapted to these and other memory architectures.
A: This depends on a number of factors such as process, density and temperature range for operation. Typically, the refresh period is tens to hundreds of microseconds in a standard CMOS process. The “SRAM-replacement” 3T-iRAM® parts feature completely hidden refresh.
A: Neither: 3T-iRAM® is best described as “port and half” memory. Each 3T bit-cell has independent read and write bit-lines and control signals, allowing some overlapping of functions. A standard 3T-iRAM bit-cell has more overlap capability than a typical single-port bit-cell, but not as much as a true dual-port bit-cell. Hence “port and a half.”
A: Current devices are 72Mb. Larger sizes are possible and may be produced based on market demand.