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Test Wafer for FaStack Prototypes

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On August 20th, 2004, the Naperville office received one test wafer from the set being built in Korea. Although this wafer was not yet ready to be stacked, the circuitry was in place and could be probed and tested with our lab equipment. Naperville engineers tested this wafer while processing continued on the rest of the wafer set.

Click on any picture to see a larger image

This is the entire wafer - about eight inches in diameter. GoldWafer.jpg (90973 bytes)
From another angle, the circuitry diffracts light into vivid colors. RainbowWafer.jpg (91045 bytes)
The wafer under a microscope; the photos below were taken through this equipment. UnderTheScope.jpg (82440 bytes)
This chip, 4 millimeters across, is an 8051-style processor. Processor.jpg (129664 bytes)
This SRAM memory chip (4mm x 4mm) can be stacked either onto the 8051-style processor to create a very fast microprocessor or onto other SRAM layers to make a 3D memory device. Memory.jpg (274520 bytes)
This is a 4mm x 4mm network of nodal interconnects. Nodes.jpg (139870 bytes)
The upper left chip is a 2mm x 2mm optical sensor array.
The lower left chip is a 2mm x 2mm register file.
On the right is a 2mm x 4mm array of multi-bit 3T-iRAM cells.
3Chips.jpg (95950 bytes)
This highly magnified view shows part of the processor chip. CloseUp3.jpg (115406 bytes)
 
Copyright © 2004-2011 Tezzaron® Semiconductor. All rights reserved.  Revised: June 03, 2011
 

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