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The documents listed here have been posted by other organizations. In many cases, Tezzaron has worked with these organizations in the research, development, or creation of 3D-ICs. Papers added since December 27 are marked with a red border like this. 2012 (alphabetical by title)3D
IC Future in Singapore 2011 (alphabetical by title)2D/3D
MAPS in the Tezzaron/Chartered Technology: Preliminary Characterization 3D
Design Using 2D Tools 3D
Digital Photodetectors 3D
IC Integration 3D-IC
Integration Developments & Cooperations for servicing 3D
Technologies for Low Power Integrated Circuits A
novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a
template for precise alignment A
Study on the Impact of Nano-Scale TSVs on 3D IC Designs A
Vertically Integrated Module Design for Track Triggers at Super-LHC Analog
front-ends for monolithic and hybrid pixels developed with a 3D CMOS process Architecture
and Performance Evaluation of 3D CMOS-NEM FPGA ASIC
and Sensor R&D Assembling
2D Blocks into 3D Chips CMC-CMP-MOSIS
collaboration for a 3D-IC prototyping service Conceptual
design of 3D integrated pixel sensors for the innermost layer of the ILC vertex
detector Designing
3D Test Wrappers for Prebond and Postbond Test of 3D Embedded Cores Development
of a Multi-Process 3D CMOS Pixel Sensor The
Economic Impact of Fermi National Accelerator Laboratory FE-I4
chip for ATLAS FEI4
chip in (3D) Chartered 130 nm The
First Multiproject Wafer Run With Chartered/Tezzaron Hardware
Accelerated Convolutional Neural Networks for Synthetic Vision Systems Heterogeneous
Thermal Simulation for Stack Vias in 3D IC Incorporating
DFT into your 3D Chip Stack Design Flow RD
Inner Tracker pour ATLAS HL LHC upgrade Signal
Integrity Analysis and Optimization for 3D ICs Technology
Transfer Testing
and Design-for-Testability Techniques for 3D Integrated Circuits Three
side buttable vertically integrated hybrid pixel detectors based on edgeless,
fully depleted sensors 2010 (alphabetical by title)3D
Circuit Design with Through-Silicon-Via: Challenges and Opportunities 3DIC
Integration with TSV – Current Progress and Future Outlook 3D-IC
MPW Runs for HEP 3DIC Multi-Project
Fabrication Run being organized by CMC/CMP/MOSIS and Tezzaron 3DIC
Multi-Project-Wafer Program: A Collaboration to Provide Fabrication Access 3D
ICs and pixel sensors: the Italian VIPIX project and the European AIDA WP3
project 3D
Motivations for High Energy Physics and for imaging devices 3D
SoC Design for H.264 Application With On-Chip DRAM Stacking 3D
technology for intelligent trackers And
now, where do we go? Application
of Vertically Integrated Electronics to Intelligent Trackers CMOS
Monolithic Pixel Sensors on high-resistivity substrate: process availability and first experimental results Cost-driven
3D Integration with Interconnect Layers Creating 3D-Specific Systems: audio/slides,
selected slides Customized Design of DRAM Controller for On-Chip 3D DRAM
Stacking Design and Analysis of
3D-MAPS: A Many-Core 3D Processor with Stacked Memory Design
and Test of 3DMAPS, a 3D DieStack ManyCore Processor Design
of DDR2 Interface for Tezzaron TSC8200A Octopus Memory intended for Chip
Stacking Applications Design
of a Monolithic Momentum Detector using a 3D IC Vertical Integration Approach Design
Platform and Tools For 3D-IC Integration Designs
and Applications of Three-Dimensional Integrated Circuits Development of fast and
high precision CMOS pixel sensors for an ILC vertex detector Efficient
distributed memory interface for Many-Core Platform with 3D stacked DRAM Efficient
OpenMP Data Mapping for Multicore Platforms with Vertically Stacked Memory Fast
readout logic interfacing a 256-pixel matrix of a dual-layer 3D device Hardware
Accelerated Convolutional Neural Networks for Synthetic Vision Systems High
Resolution CMOS Pixel Sensor for the STAR Vertex Detector Upgrade High
Sensitivity Fully Digital Photodetector Junction-level
Thermal Extraction and Simulation of 3DICs Logic-on-Logic
3D Integration and Placement Modeling
TSV Open Defects in 3D-Stacked DRAM More
Than Moore NCSU
Tezzaron Design Kit Pixel:
A Résumé Pixel
Detectors in 3D Technologies for High Energy Physics Processor
Architecture Design Using 3D Integration Technology Scalable
Event Routing in Hierarchical Neural Array Architecture with Global Synaptic
Connectivity Sparsified
Fast Readout for a 256-Pixel 3D Device Tezzaron-Chartered
3D-IT electronic for SLHC/ATLAS pixels Thin
Pixel development for the SuperB Silicon Vertex Tracker Through-Silicon-Via
Based 3D IC Research Activities at the Georgia Tech Computer-Aided Design Laboratory Towards
a high performance vertex detector based on 3D integration of deep N-well MAPS TSV-Aware
3D Physical Design Tool Needs for Faster Mainstream Acceptance of 3D ICs Vertically Integrated
Pixel Readout Device for the Vertex Detector at the International Linear Collider Wafer-Level
3D ICs: Technology Platforms and Applications 2009 (alphabetical by title)3D
design activities at Fermilab — Opportunities for physics 3D
electronics for hybrid pixel detectors 3-D integration
technologies: The new challenge of Hybrid Pixels detectors CMOS Pixel
Sensors and Mixed-Signal Readout Electronics In a 3D Integration Technology Design
of DDR2 Interface for Tezzaron TSC8200A Octopus Memory intended for Chip
Stacking Applications Development
of Vertically Integrated Circuits for Particle Detectors Exploring
Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and
Durable Memory Architectures MAPS
with pixel level sparsified readout: from standard CMOS to vertical integration OMEGAPIX: 3D
integrated circuit prototype dedicated to the ATLAS upgrade Super LHC pixel
project On-Chip
Fast Readout Sparsification for a 256-Pixel 3D Device Opportunities for HEP Instrumentation Using 3D Circuits Routerless
System Level Interconnection Network for 3D Integrated Systems Thin, Fully Depleted Monolithic Active Pixel Sensor based on 3D
Integration of Heterogeneous CMOS Layers Variation-Tolerant
Non-Uniform 3D Cache Management in Die Stacked Multicore Processor Vertically
Integrated Circuits at Fermilab Copyright ©2010-2012 Tezzaron® Semiconductor. All rights reserved. Revised: January 03, 2012 |
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