 |
Error-resistant
3T-iRAM® technology |
|
DTRII™
Interface with Separate I/O buses |
|
Fully
pin-compatible with DDRII and SigmaSIO-II™ SRAMs |
|
Lead-free
JEDEC-standard
pinout and package |
|
Burst
of 2 Read and Write (Byte Writes) |
|
1.8
V +100/–100 mV core power supply |
|
1.5
V or 1.8 V HSTL Interface |
|
Synchronous
internally self-timed Writes |
|
Fully
coherent read and write pipelines |
|
ZQ
pin for programmable output drive strength |
|
IEEE
1149.1 JTAG-compliant Boundary Scan |
|
165-bump
15mm x 17mm BGA, 1 mm bump pitch |
|
Pin-compatible
with 9Mb, 18Mb, 36Mb, and 144Mb devices |
3T-iRAM® is a unique type
of dynamic memory. Tezzaron has crafted these pseudo-static devices to
provide entirely SRAM-compatible interfaces and timing. The unique design
of these 3T memories provides soft error rates up to 10 times lower than
equivalent high-speed, high-density SRAMs.
DTRII™ is a double
transfer rate interface that is implemented with Separate I/O architecture
in these devices, making them drop-in compatible with DDRII and SigmaSIO-II™
SRAMs.
These synchronous 72Mb
3T-iRAM devices employ two input register clocks
. The user can manipulate the two output register clocks
quasi-independently
. These clocks are four independent single-ended clock inputs, not
differential inputs. If the output clocks are tied high, the input clocks
are routed internally to fire the output registers instead.
These devices always transfer data in two packets, but
addressing is handled differently for x9 parts than for x36 and x18 parts:
For x36 and x18, when a new address is loaded, A0
presets an internal 1 bit address counter. The counter increments by 1
(toggles) for each beat of a burst of two data transfer.
For
x9, when a new address is loaded, the LSB is internally set to 0 for the
first read or write transfer, and incremented by 1 for the next
transfer.
