 |
Error-resistant
3T-iRAM® technology |
|
Multi-level
Bit Armor™ data protection (internal ECC, periodic scrubbing,
error reporting) |
|
NBT
(No Bus Turnaround) functionality for zero wait Read-Write-Read bus
usage |
|
Fully
pin-compatible with pipelined NtRAM™, NoBL™ and ZBT™ |
|
1.8
V ± 0.1 V core power supply, 1.8 V or 2.5 V I/O supply |
|
LODRV pin for user-selectable
drive strength |
|
IEEE
1149.1 JTAG-compatible Boundary Scan |
|
User-selectable
Linear or Interleaved Burst mode |
|
Pin-compatible
with 2/4/9/18/36Mb devices |
|
Byte
write operation (9-bit Bytes) |
|
3
Chip Enable signals for easy depth expansion |
|
ZZ
pin for automatic power-down |
|
Lead-free JEDEC standard 165-FBGA package |
3T-iRAM® is a unique type
of dynamic memory. Tezzaron has crafted these pseudostatic devices to
provide entirely SRAM-compatible interfaces and timing. The unique design
of these 3T memories provides soft error rates up to 10 times lower than
equivalent high-speed, high-density SRAMs. In addition, these parts
incorporate Tezzaron’s multi-level Bit Armor™ system for error rates
up to 1000 times lower than traditional SRAMs. Bit Armor incorporates
user-transparent periodic error scrubbing and ECC with error reporting.
The TSC3E72T18/36 is a
72Mbit synchronous memory device that functions much like ZBT, NtRAM, NoBL,
and other pipelined read/double late write SRAMs – it exploits all
available bus bandwidth by eliminating “deselect cycles” when the
device is switched from read to write.
As in all synchronous devices, address, data inputs, and
read/write control inputs are captured on the rising clock edge. The burst
order control pin must be tied to a power rail for proper operation.
Asynchronous inputs include Sleep mode enable and Output Enable. Output
Enable can override the synchronous control of the output drivers to turn
them off at any time. Write cycles are internally self-timed and initiated
by the rising clock edge; this eliminates the complex off-chip write pulse
generation required by asynchronous SRAMs and simplifies input signal
timing.
The
TSC3E72T18/36 incorporates a rising-edge-triggered output register. For
read cycles, output data is stored in the edge-triggered output register
during the access cycle and then released to the output drivers at the
next rising clock edge.
|
Parameter
Synopsis:
|
|
|
-250
|
-200
|
-166
|
Unit
|
|
|
3-1-1-1
|
tKQ
|
2.5
|
3.0
|
3.5
|
ns
|
|
|
tCycle
|
4.0
|
5.0
|
6.0
|
ns
|
|
|
Curr
|
tbd
|
tbd
|
tbd
|
mA
|
