 |
Error-resistant
3T-iRAM® technology |
|
Dual
DDRII Interface |
|
Pin-compatible
with QDRII™ and SigmaQuad-II™ SRAMs |
|
Lead-free
JEDEC-standard
pinout and package |
|
Burst
of 2 Read and Write |
|
Separate
independent Read and Write data ports |
|
Concurrent
Read/Write transactions are supported |
|
Separate
Port Selects for depth expansion |
|
Synchronous
internally self-timed Writes |
|
1.8
V +100/–100 mV core power supply |
|
Expanded
HSTL output voltage: 1.4 V to 1.9 V |
|
Fully
coherent read and write pipelines |
|
ZQ
pin for programmable output drive strength |
|
IEEE
1149.1 JTAG-compliant Boundary Scan |
|
165-bump
15mm x 17mm BGA, 1 mm bump pitch |
|
Pin-compatible
with 9Mb, 18Mb, 36Mb, and 144Mb devices |
3T-iRAM® is a unique type
of dynamic memory. Tezzaron has crafted these pseudo-static devices to
provide entirely SRAM-compatible interfaces and timing. The unique design
of these 3T memories provides soft error rates up to 10 times lower than
equivalent high-speed, high-density SRAMs, while maintaining drop-in
compatibility.
QTR™ (Quad Transfer Rate)
is a Separate I/O architecture that makes these devices drop-in compatible
with QDRII™ and SigmaQuad-II™ SRAMs. It accesses the memory array with
two separate ports for Read and Write operations, using dedicated data
input and output pins and a common address bus. This completely eliminates
the “bus turn-around” time required in Common I/O devices. To maximize
throughput, both data ports use DTRII™ (Double Transfer Rate) interfaces.
These pipelined synchronous
72Mb devices employ two input register clocks
. The user can manipulate two output register clocks
quasi-independently
. All four of these clocks are independent single-ended clock
inputs, not differential inputs, for precise data timing. If the output
clocks are tied high, the input clocks are routed internally to fire the
output registers instead.
These devices always transfer data in two packets. A0 is
internally set to 0 for the first data transfer of a burst and
automatically incremented to 1 for the second transfer.
