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Error-resistant 3T-iRAM® technology |
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Dual DDRII Interface |
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Pin-compatible with QDRII™ and SigmaQuad-II™ SRAMs |
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Lead-free JEDEC-standard pinout and package |
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Burst of 4 Read and Write |
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Separate independent Read and Write data ports |
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Concurrent Read/Write transactions are supported |
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Separate Port Selects for depth expansion |
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Synchronous internally self-timed Writes |
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1.8 V +100/–100 mV core power supply |
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Expanded HSTL output voltage: 1.4 V to 1.9 V |
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Fully coherent read and write pipelines |
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ZQ pin for programmable output drive strength |
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IEEE 1149.1 JTAG-compliant Boundary Scan |
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165-bump 15mm x 17mm BGA, 1 mm bump pitch |
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Pin-compatible with 9Mb, 18Mb, 36Mb, and 144Mb devices |
3T-iRAM® is a unique type of dynamic memory. Tezzaron has crafted these pseudo-static devices
to provide entirely SRAM-compatible interfaces and timing. The unique design of these 3T
memories provides soft error rates up to 10 times lower than equivalent high-speed,
high-density SRAMs, while maintaining drop-in compatibility.
QTR™ (Quad Transfer Rate) is a Separate I/O architecture that makes these devices drop-in
compatible with QDRII™ and SigmaQuad-II™ SRAMs. It accesses the memory array with two separate
ports for Read and Write operations, using dedicated data input and output pins and a common
address bus. This completely eliminates the “bus turn-around” time required in Common I/O
devices. To maximize throughput, both data ports use DTRII™ (Double Transfer Rate) interfaces.
These pipelined synchronous 72Mb devices employ two input register clocks. The user can
manipulate two output register clocks quasi-independently. All four of these clocks are
independent single-ended clock inputs, not differential inputs, for precise data timing. If
the output clocks are tied high, the input clocks are routed internally to fire the output
registers instead.
These devices always transfer data in four packets. A0 and A1 are internally set to 0 for the
first read or write transfer and automatically incremented by 1 for each of the next three
transfers.
