72Mb Synchronous Quad Transfer Rate (QTRII™ ) 3T-iRAM®, Burst of 4, 2.0 Cycle Read Latency; SRAM-Compatible

3T-iRAM® is a unique type of dynamic memory. Tezzaron has crafted these pseudo-static devices to provide entirely SRAM-compatible interfaces and timing. The unique design of these 3T memories provides soft error rates up to 10 times lower than equivalent high-speed, high-density SRAMs, while maintaining drop-in compatibility.

QTRII+™ (Quad Transfer Rate II+) is a Separate I/O architecture that makes these devices drop-in compatible with QDRII+™ SRAMs. It uses two separate ports for Read and Write operations with dedicated data input and output pins and a common address bus. This completely eliminates the “bus turn-around” time required in Common I/O devices. To maximize throughput, both data ports use DTRII+™ (Double Transfer Rate II+) interfaces.

These pipelined synchronous 72Mb devices employ two input register "K" clocks. These are independent single-ended clock inputs, not differential inputs, for precise data timing. Read and Write addresses are latched on alternate rising edges of the K clock. Data transfers (input and/or output) occur on the rising edges of both clocks. Two echo clocks simplify data capture for Reads. Writes are self-timed with on-chip circuitry.

These devices always transfer data in four packets. A0 and A1 are internally set to 0 for the first read or write transfer and automatically incremented by 1 for each of the next three transfers.