 |
Memory
widths: x64, x16, x8, and x4 (64, 16, 8, or 4 data bits per data
transfer) |
|
Lead-free
BGA
Package |
|
Conforms
to JEDEC specification "JESD79", definition DDR-266A |
|
Fastest
versions use HyperDDR333 timing (tRAS = 27 ns tRFC = 36 ns) |
|
Double-Data-Rate
(DDR) architecture: two data transfers per clock cycle |
|
Bidirectional
data strobes |
|
Differential
clock inputs |
|
DLL
aligns data and strobe signals with CK for read and write operations
(edge-aligned for read, center-aligned for write) |
|
Four
internal banks, concurrent operation |
|
Auto-Precharge
option for each burst |
|
Read
Latency: 2 or 2.5 cycles |
|
Auto-Refresh
and Self-Refresh modes |
|
7.8
ms maximum average periodic refresh interval (8k/64ms) |
|
2.5
V I/O (SSTL_2 compatible) |
|
VDD
= +2.5 V ±0.2 V, VDDQ = +2.5 V ±0.2 V |
|
Maximum
burst refresh cycle: 8 |
|
Burst
types: sequential & interleaved |
|
Burst
lengths: 2, 4, or 8 locations |
The Leo FaStack® is an integrated circuit that performs
as a DDR SDRAM, compatible with the JEDEC DDR I standard, and
incorporating features above and beyond that standard. It acts as a
high-speed, CMOS, dynamic random-access memory containing 1,073,741,824
bits, configured internally as a quad-bank DRAM. It achieves high-speed
operation through a double-data-rate (DDR) architecture - that is, a 2n
pre-fetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. Each read or write access consists
of a single data transfer (two data words in one clock cycle) at the
internal DRAM core, and two corresponding data transfers (each being one
data word in one-half clock cycle) at the I/O pins.
A bidirectional data strobe is transmitted externally
along with each byte of data for use in data capture at the receiver. Each
strobe signal is edge-aligned and transmitted by the DDR SDRAM for reads;
it is center-aligned and transmitted by the memory controller for writes.
The 64-bit Leo FaStack has eight data strobes, one for each byte; the
16-bit version has 2 data strobes; the 8-bit and 4-bit versions use a
single data strobe.
The Leo FaStack operates from a differential clock.
Commands (address and control signals) are registered at every positive
edge of CK. Input data are registered on both strobe edges; output data
are registered to both edges of the strobe as well as to both edges of the
clock.
Read and write accesses are burst oriented; each access
starts at a selected location and continues for a programmed number of
locations in a programmed sequence. An access begins with the registration
of an ACTIVATE command, which is then followed by a READ or WRITE command.
In all three commands, the bank address bits define the bank to be
accessed; the address bus bits registered with the ACTIVATE command define
the row to be accessed; the address bus bits registered with the READ or
WRITE command define the starting column for the burst access.
Read or write bursts may be programmed for a length of
2, 4, or 8 locations. Enabling the Auto-Precharge function provides a
self-timed row precharge that is initiated at the end of the burst access.
The pipelined multi-bank architecture hides row precharge and activation
time by allowing concurrent operation, thereby providing high effective
bandwidth.
Available modes include Auto-Refresh and Power-Down. All
inputs are compatible with the JEDEC SSTL_2 standard; outputs are
compatible with the JEDEC SSTL_2, Class II standard.
