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Memory widths: x16, x8, and x4 |
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Lead-free FBGA Package |
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Conforms to JEDEC specification "JESD79-2" with additional features |
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Fastest versions use HyperDDR timing |
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Double-Data-Rate (DDR) architecture: two data transfers per clock cycle |
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Differential data strobe (optional use) |
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Differential clock inputs |
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DLL aligns data and strobe signals with CK for read and write operations (edge-aligned for
read, center-aligned for write) |
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Eight banks, concurrent operation |
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Hidden precharge |
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Programmable Latency: 2 to 6 clock cycles |
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Self-Refresh and Power-Down modes |
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Programmable output drive strength |
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On-Die termination (ODT) |
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On-chip temperature detection |
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8,192-cycle refresh: 64 ms for normal temp, 32 ms for high temp |
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Maximum of 8 back-to-back REFRESH operations |
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1.8 V I/O (SSTL_18 compatible) |
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VDD and VDDQ = +1.8 V ±0.1 V |
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Burst types: sequential or interleaved |
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Burst lengths: 4 or 8 (programmable) |
Leo II is a DDR3 SDRAM built in the FaStack® wafer stacking process. It is compatible with the
JEDEC DDR3 standard and incorporates features above and beyond that standard. Leo II is a
three-dimensional integrated circuit (3D IC) which acts as a high-speed dynamic random-access
CMOS memory containing 1, 2, or 4 Gigabits, configured internally as an 8-bank DRAM. It
achieves high-speed operation through a double-data-rate (DDR) architecture - that is, it
transfers two data words per clock cycle at the I/O pins.
At least one bidirectional data strobe is transmitted externally along with the data for use
in data capture at the receiver. Each strobe signal is edge-aligned and transmitted by the
Leo II for reads; it is center-aligned and transmitted by the memory controller for writes.
The 16-bit Leo II has two data strobes, one for each byte; the 4-bit version Leo II uses a
single data strobe. The 8-bit version has two data strobes and can be configured to use one or
both. All data strobes have complementary signals for differential pair signaling; their use
is optional.
The Leo II operates from a differential clock. Commands (address and control signals) are
registered at every rising edge of CK. Input data are registered on both edges of the strobe;
output data are registered to both edges of the strobe as well as to both edges of the clock.
Read and write accesses are burst oriented; each access starts at a selected location and
continues for either 4 or 8 locations in a programmed sequence. Access begins with the
registration of an ACTIVATE command, which is then followed by READ and/or WRITE commands. In
all three commands, the bank address bits define the bank to be accessed; the address bus bits
registered with the ACTIVATE command define the row to be accessed; the address bus bits
registered with each READ or WRITE command define the starting column for each burst access.
Bursts of 4 cannot be interrupted. Bursts of 8 can be interrupted by another command of the
same type - that is, a read burst may be interrupted by a new READ command, and a write burst
can be interrupted by a new WRITE command. In these cases, the original burst of 8 is
abandoned after the 4th data transfer.
Unlike other DDR3 devices, the Leo II does not require PRECHARGE commands. The PRECHARGE
command is supported for purposes of compatibility, but it performs as a NOP.
The pipelined multi-bank architecture hides row activation time by allowing concurrent
operation, thereby providing high effective bandwidth.
Available modes include Self-Refresh mode (to retain data without external clocking) and
Power-Down mode (to save power).
All inputs are compatible with the JEDEC SSTL_18 standard; at full drive strength, all
outputs are compatible with the JEDEC SSTL_18 standard.
