For papers and articles discussing 3D ICs, we recommend the Literature Page at the website of the 3D-IC Alliance.

The information below is gathered from trade publications, websites, and conference presentations. Please alert us to any corrections and updates at webmaster@tezzaron.com.

Page contents:

3D-IC Products and Services

FaStack® wafer-to-wafer and die-to-wafer stacking, Cu-Cu thermo-compression; copper and tungsten TSVs.  3D products, custom 3D designs, 3D multi-project wafers, joint ventures, 3D prototyping, and licensing. Research on 2.5D (with IME A*STAR) and rad-hard 3D-ICs (with Honeywell). (2012)

DBI® wafer-to-wafer and die-to-wafer stacking, room-temperature covalent bonding (silicon fusion) and direct oxide bonding; heterogeneous substrates; custom 3D services. (2012)

Permanent 3D memories, one-time-programmable (OTP); multiple memory layers built on a single wafer. (2011)

"Micro-bump" stacking; specializes in image sensors. (2010)

VIP™ vertical connectors applied to die edges; 3D packaging. (2010)

3D-related services: wafer bumping, 3D packaging etc. (2010)

3D chip packaging, wafer support & processing, bonding, assembly, finishing, etc. (2012)

Standard die stacking; rebuilt wafer stacking; no TSVs. (2010)

Through-silicon via (TSV) foundry services. (2011)

Provides TSV manufacturing for its foundry customers. (2010)

Nonprofit; organizes 3D multi-project wafers (MPWs) for Canadian universities (with MOSIS and Tezzaron). (2012)

Organizes 3D multi-project wafers (MPWs), with MOSIS and Tezzaron. (2012)

Organizes 3D multi-project wafers (MPWs), with Tezzaron. (2012)

Foundry services including TSVs. (2010)

TSVs, interposers, wafer-level packaging. (2011)

3D-IC services: design, layout, interconnection, TSVs, assembly, testing, packaging. (2012)

Temporary wafer bonding, wafer thinning, thin wafer processing. (2012)

Programmable 3D devices (FPGAs). (2012)

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3D Tools, Materials, & Equipment (in alphabetical order)

Wafer thinning system, adhesives, CMP solutions (2011)

Licenses nanometric electrochemical deposition technology for TSV. (2011)

TSV manufacturing flows, etch technology. Collaborations with imec, EVG, IME A*STAR. (2012)

Thin wafer handling, bonding/debonding technologies, ZoneBOND technology (with EVG, SUSS). (2011)

Materials and equipment for 3D - dicers, adhesives, etc. (2010)

Equipment for thin wafer dicing. (2010)

Equipment for alignment, permanent bonding, temporary bonding & de-bonding. (2012)

3D metrology and inspection solutions (2011)

Provider of TSV-enabled wafers.  Works with SEMATECH. (2012)

3D-IC etch system for TSV. (2010)

EDA tools & Tessent test tool for 3D-ICs. (2012)

MAX-3D layout editor for 3D-IC designs, TSV floor-planner, other 3D-IC EDA tools. (2012)

Wafer-to-wafer bonding metrology tool. (2011)

Plasma processing equipment for  3D through-silicon vias (TSVs). (2010)

Electrochemical deposition (ECD) and physical vapor deposition (PVD) systems (2012)

3D-IC Automated Metrology System (2010)

Plasma equipment for wafer thinning. (2010)

EDA tools for 3D integrated circuit design and analysis; 3D circuit design services. (2010)

Chip placement systems, chip-to-chip and chip-to-wafer bonders. (2012)

Deep silicon etch systems for TSV. (2010)

Aligners, wafer and device bonders, thin-wafer processes, temporary bonding & debonding, other 3D packaging tools. (2012)

Metrology system for 3DIC packaging & process development (2012)

Scanners, steppers, aligners, lasers, etc. (2011)

Plasma etch and deposition systems, silicon DRIE tools (2010)

3D packaging tools: TSV deep-silicon etch, advanced deposition, wafer bonder/debonder (2012)

Lithography steppers for 3-D technologies. (2010)

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3D IC Research (in alphabetical order)

Consortium of integrated circuit designers, developers, and manufacturers; promotes standards for 3D ICs. (2010)

Research on automated test and handling solutions for 3D and 2.5D TSV stacks. (2012)

Research on wafer stacking, alignment, TSVs, bonding, etc; partner with SEMATECH and other research groups. (2010)

Research (with TSMC) on FPGAs, etc., using 2.5D interposers. (2012)

Research on power, noise, and thermal testing of 3D ICs (2010)

3D Research collaboration with IME A*STAR. (2012)

Research on 3D-related packaging, copper bonding, TSV (with SEMATECH). (2011)

Japanese consortium performing "dream chip" R&D including interposers, TSV, reconfigurable 3D, etc. (2010).

Developing 3D-IC design tools, including pathfinding; announced working 3D design flow.  (2012)

Developing 3D-IC design tools; announced working 3D design flow (with Atrenta).  (2010)

Research on 3D memories and image sensors without using TSV. (2010)

Developing 3D IC design & test tools, wide I/O memory core; collaborating with TSMC on 3D-IC design infrastructure. (2012)

Research (with imec) on 3D test issues. (2011)

Research on many 3D-IC technologies including 3D nanophotonic devices; die-on-wafer and wafer-on-wafer bonding.  Collaborations with Atrenta, Cadence, Docea, IPDiA, Presto, R3Logic, SET, SPTS, etc. (2011)

Funds special research, including 3D IC process technology, heterogeneous integration, 3D architectures, stacked FPGAs, etc. (2010)

Research on chip-to-wafer bonding (2011).

Research on 3D-ICs; now offering wafer-scale packaging. (2011)

Research on temporary bonding materials (with Suss) (2012)

Research on materials & processes for 3D-ICs. (2010)

Research on semiconductor packaging & circuit materials (2010)

 Research on many facets of 3D ICs, working with IBM and Boston U. (2010)

Research on high-density memories, via-first, back-bumping,  interposer layer, and interface chip. Teamed with Powertech Technology (PTI) and United Microelectronics Corporation (UMC) (2011)

Research on Z-axis interconnect. (2010)

Research on 3D components, particularly sensors and detectors; sponsors multi-participant research projects; sponsored Pixel 2008; 2009, sponsoring a 3D MPW (multi-project wafer) with other particle detector groups. (2010)

Research on 3D imagers. (2010)

Research on many types of 3D integration, interconnection, and assembly, including TSV formation, temporary wafer bonding, debonding, testing; 3D integration of memory, logic, analog, MEMS, and RF. (2012)

Research on physical design, design tools, micro-architecture, thermal issues, and testing in 3D ICs; research on 3D interconnect, packaging, interposers; hosts Interconnect & Packaging Center (IPC) and Packaging Research Center (PRC); announced new 3D ThinPack consortium. (2012)

Research to promote adoption of 3D; markets, tools, interfaces, testing, and standards. (2011)

Research on adhesives for temporary and permanent wafer bonding, thin wafer handling. (2010)

Research on process and design technology for 3D stacking. (2010)

Research (with Tezzaron) on rad-hard 3D-ICs. (2012)

Research on 3D interconnect, TSV, memories, sensors, interposers. (2012)

Research (with SEMATECH) on 3D design tools, test structures, methodology, process, infrastructure, cooling, interposers, via-middle TSV (annular?) etc.  Collaboration with Micron on 3D memory. Some products in production with low-density TSVs. (2012)

Produces publications, workshops, conferences, etc. (2012) 

Research on many aspects of 3D IC technology including TSVs, thinning, bonding, cooling, interconnects, interposers, and 2.5D; research collaboration with Applied Materials, UMC, others. (2012)

Research on many 3D-IC approaches and technologies including thermal models, design tools, test issues, wafer-level packaging. (2012)

Research into many areas of 3D IC technology. (2010). 

Pure-play MEMS foundry, researching TSVs for 3D ICs. (2010)

Research (with ITRI) on 3D memory and (with SEMATECH) on many applications of 3D IC technology. (2011)

 Research on 3D integration of passives (with CEA-Leti); also TSVs, including an MPW. (2011)

Research on 3D IC process technology and thermal issues, 3D modular system integration, interconnects by die-edge metallization and thru-silicon (not thru-die) vias; 3D imagers. (2011)

Research (with A*STAR IME) on TSV substrates. (2011)

Research on stacking, both C2C and W2W; TSVs and micro-bumps; 3D-IC standards.  Leads Ad-STAC consortium; research (with Intel) on 3D memory. (2011)

Research on standards for 3D-ICs, notably the Wide I/O memory standard. (2011)

Research on modeling & measurement of 3D ICs;  also interposers. (2010)

Research on SOI wafer stacking with low-temperature oxide bonding; 3D advanced focal-plane arrays; participated in several DARPA MPWs. (2011)

Research on 3D-IC high-energy particle detectors (2011)

Announced "Hyper Memory Cube" (with IBM) using TSV, solder balls, 4 layers of DRAM and a logic layer; working on "Hybrid Memory Cube" (with Samsung). (2012)

Research on 3D IC layout methodology, wafer stacking, high-density interconnect, copper bonding, oxide fusion bonding, 3D imagers. (2010)

Research on monolithic 3D chips with no TSVs. (2011)

Research on 3D stacking, sensors, memories, and packaging. (2011)

Research on thermal management for 3D ICs (2010)

Research on 3D interconnect networks, applications, architectures, & design rules. Working with DARPA; SRC award for research. (2011)

Research on ultra-thin wafer handling, TSVs. (2010)

Research on using Aerosol Jet® material deposition system for vertical interconnect. (2011)

Research into 3D-IC design, tools, and architecture. (2011)

Research on 3D IC packaging technologies; teamed with Elpida and United Microelectronics Corporation (UMC). (2011)

Research on low-cost, low-power, reliability, and heterogeneous 3D-ICs. (2011)

Research (with imec, SEMATECH) on 3D design tools & technologies, MEOL processes, TSV, 3D memory. (2012)

Research on SiP, die-on-wafer stacking, TSVs. (2012) 

Research on many aspects of 3D-IC design, interconnect, manufacturing.  (2011)

Provides research and technical expertise to governments and businesses on many 3D-IC technologies. (2010)

Research (with SEMATECH and OSAT) on process characterization, process control, metrology, and inspection (2010).

Research (with SEMATECH) on chip-on-chip and chip-on-wafer stacking for high-density memory; thru-silicon vias (TSV), micro-bumps; applications. Announced wide I/O DRAM with TSV for mobile devices; "Hybrid Memory Cube" (with Micron). (2011)

Research on interposers; TSVs; bonding; radiation effects in 3D-ICs. (2011)

Fosters research on many 3D-IC issues including bonding/debonding, wafer thinning, 3D standards, equipment, applications, and a pilot line; organizes symposiums and conferences; maintains semiconductor industry roadmap (2012)

Runs an International Standards program that includes research on 3D-IC standards. (2011)

Research (with EVG) on temporary wafer bonding and de-bonding. (2012)

International consortium to improve interoperability and integration across silicon design flows.  For 3D: power distribution, thermal design, design constraints, and design for test. (2012)

Research on 3D standards and applications. (2011)

Research on 3D EDA tools (2012)

Research on wafer-level circuit stacking, mostly SOI wafers, using handler wafers and low-temperature oxide-oxide molecular bonding. Also working with CEA-Leti. (2010)

Research and low-volume production on 3D backside-illumination technology in stacked CMOS sensors. (2012)

Coordinates academic "pre-competitive" research, including 3D process structures, standards, applications, integration, reliability, and tools. (2011)

Research on 3D for mobile phones, Wide-IO DRAM, and full 3D-IC integration for wireless technology. (2011)

Research on 3D IC interconnects, integrity, performance, epitaxial growth, thermal issues, hybrid devices, 3D FPGAs, etc. (2010)

Research on TSVs, micro-bumping, interposers, thin wafer handling, embedded ball grid. (2012)

Research on wafer-level and chip-level alignment; covalent bonding; vertical communication bit-rates; 3D CMOS image sensors; etc (with CEA-Leti, SET, etc.). (2011)

Research on 3D-IC package development and wafer-level processing. (2011)

Research on interposers, TSVs (with imec); initiative for 3D-IC EDA tools. (2012)

Developing 3D chip-scale packaging for sensors using TSV and "glass sandwich," also wafer-level technologies to enable stacking. Purchased 3D-IC patents and technology from Allvia; doing joint R&D. (2011)

Research on 3D-ICs with TSV, wide I/O memory architecture. (2011)

Research on wafer stacking with adhesive, die-to-wafer bonding with self-assembly, and mechanical stress and contamination issues; developed a 3D artificial retina. (2011)

Research (with SEMATECH) on 3D interconnect and (with SEMI) 3D standards. (2011)

Research on chip-stacking with copper bump bonding and TSV; 3D NAND Flash; 3D memory cells and CCDs (tested 2005). (2011)

Research on 3D-IC fabrication, design, packaging, and testing; also silicon interposers for 2.5D devices (with Altera). Announced intent to perform beginning-to-end 3D processing for customers; collaborating with Cadence on 3D-IC design infrastructure. (2012)

Research on 3D thermal-aware design automation (with DARPA, CFDRC). (2011)

3D foundry research; teamed with Elpida, PowerTech, SEMATECH, IME A*STAR. (2012)

Research on vertically integrated pixel detector (2011)

Research on 3D silicon pixel sensors for high energy physics (2011)

Research on 3D-IC active pixel sensors (2010)

Research on TSV, clock & power distribution in 3D ICs. (2010)

Research on interconnect reliability. (2010)

Research on 3D NAND Flash, bumpless wafer stacking (2011)

Research on die stacking; vertical connectors are applied to the die edges. (2010)

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Market Research, Analysis, Consulting, Reporting

An interactive web community in support of 3D integration technologies (2011)

Maintains an index of recent articles and news stories (2011)

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